From 23470142e8749f71e3136c2da4716e12011d2f77 Mon Sep 17 00:00:00 2001 From: Kyle Gunger Date: Mon, 29 Apr 2024 14:36:02 -0400 Subject: Add board schematic --- board/project/jobs.lp | 24 ++++++++++++++++++++++++ board/project/metadata.lp | 6 ++++++ board/project/settings.lp | 10 ++++++++++ 3 files changed, 40 insertions(+) create mode 100644 board/project/jobs.lp create mode 100644 board/project/metadata.lp create mode 100644 board/project/settings.lp (limited to 'board/project') diff --git a/board/project/jobs.lp b/board/project/jobs.lp new file mode 100644 index 0000000..0454210 --- /dev/null +++ b/board/project/jobs.lp @@ -0,0 +1,24 @@ +(librepcb_jobs + (job 1ff24f7c-ee1a-4ea0-ab33-9c75ea7480a3 (name "Gerber/Excellon") + (type gerber_excellon) + (outlines (suffix "_OUTLINES.gbr")) + (copper_top (suffix "_COPPER-TOP.gbr")) + (copper_inner (suffix "_COPPER-IN{{CU_LAYER}}.gbr")) + (copper_bot (suffix "_COPPER-BOTTOM.gbr")) + (soldermask_top (suffix "_SOLDERMASK-TOP.gbr")) + (soldermask_bot (suffix "_SOLDERMASK-BOTTOM.gbr")) + (silkscreen_top (suffix "_SILKSCREEN-TOP.gbr")) + (silkscreen_bot (suffix "_SILKSCREEN-BOTTOM.gbr")) + (solderpaste_top (create true) (suffix "_SOLDERPASTE-TOP.gbr")) + (solderpaste_bot (create true) (suffix "_SOLDERPASTE-BOTTOM.gbr")) + (drills (merge false) + (suffix_pth "_DRILLS-PTH.drl") + (suffix_npth "_DRILLS-NPTH.drl") + (suffix_merged "_DRILLS.drl") + (suffix_buried "_DRILLS-PLATED-{{START_LAYER}}-{{END_LAYER}}.drl") + (g85_slots false) + ) + (board default) + (output "gerber/{{PROJECT}}_{{VERSION}}") + ) +) diff --git a/board/project/metadata.lp b/board/project/metadata.lp new file mode 100644 index 0000000..af03d10 --- /dev/null +++ b/board/project/metadata.lp @@ -0,0 +1,6 @@ +(librepcb_project_metadata 2477e3ed-3141-4931-a80f-b73196a59879 + (name "OSm Thermal") + (author "Kyle Gunger") + (version "v1.5") + (created 2024-04-16T01:13:30Z) +) diff --git a/board/project/settings.lp b/board/project/settings.lp new file mode 100644 index 0000000..95ff1f5 --- /dev/null +++ b/board/project/settings.lp @@ -0,0 +1,10 @@ +(librepcb_project_settings + (library_locale_order + ) + (library_norm_order + (norm "IEEE 315") + ) + (custom_bom_attributes + ) + (default_lock_component_assembly false) +) -- cgit v1.2.3